1. Field of the Invention
The present invention relates to a zener zap diode having a construction in which a conductive layer such as a polycrystalline silicon layer is formed on an outer base region constituting a base region and a contact between the conductive layer and a metal interconnecting layer for a base electrode is formed.
2. Description of Related Art
FIG. 1 illustrates a construction of a conventional zener zap diode formed at the same time with bipolar transistors, which will now be described using the references of parts from the bipolar transistor formed at the same time with the zener zap diode. In this figure, a device isolation film 103 by means of the LOCOS (Local Oxidation of Silicon) method is selectively formed in an N-type well region 102 formed on a P-type silicon substrate 101. An insulation film 104 for determining an area in which an outer base region 107 of a P-type described later is formed is selectively formed on the device isolation film 103 and the N-type well region 102. Furthermore, a first polysilicon layer 105 as a base lead electrode is formed so as to partially cover the insulation film 104. The polysilicon layer 105 is overlaid with a field insulation film 106.
The outer base region 107 which is made of a P-type impurity diffusion layer and constitutes a base region, and an active base region 108 are formed in areas adjacent to the surface of the silicon substrate 101 determined by the insulation film 104. An emitter region 109 made of an N-type impurity diffusion layer is formed in the silicon substrate 101 on the upper side of the active base region 108. The emitter region 109 and the active base region 108 constitute a PN junction of the zener zap diode.
A pit 110 reaching the emitter region 109 through the polysilicon layer 105 and the field insulation film 106 is formed on the upper side of the emitter region 109. A side wall insulation film 111 made of a silicon oxide film is formed around the inner wall of the pit 110 to completely isolate the emitter region 109 from the polysilicon layer 105.
A second polysilicon layer 112 as an emitter lead electrode is formed on the emitter region 109 and is extended to overlay the side wall 111 and a part of the field insulation film 106. A metal interconnecting layer 113-1 for connecting the emitter lead electrode is selectively formed on the polysilicon layer 112.
The first polysilicon layer 105 extends to the upper surface of the insulation film 104 formed on the device isolation film 103. A pit 114 reaching the polysilicon layer 105 is provided with the field insulation film 106 above the device isolation film 103. Forming the pit 114 gives a contact 114a between the polysilicon layer 105 and a metal interconnecting layer 113-2 for the base.
Thus, in the conventional zener zap diode, to reduce the parasitic capacity of the outer base region 107, the contact 114a between the first polysilicon layer 105 connected to the outer base region 107 and the metal interconnecting layer 113-2 has been disposed above the device isolation film 103.
In the manufacturing process of the integrated circuit (IC) comprising multiple semiconductor devices such as bipolar transistors and zener zap diodes, the so-called trimming process is a common exercise. The trimming process is conducted to save the IC chip from being disposed as totally defective due to a partial failure of the semiconductors. Namely, when there is a partial failure among the multiple semiconductor devices formed on one IC chip, the junctions configuring the semiconductor devices in failure are cut off, or on the contrary, short-circuited to change the defective semiconductor devices into resistors; thus saving the total of the IC chip. Especially when the semiconductor devices are zener zap diodes, the method called zener zap trimming is applied.
However, in the conventional zener zap diode in which the contact r a between the first polysilicon layer 105 connected to the outer base region 107 and the metal interconnecting layer 113-2 is disposed above the device isolation film 103, as shown in FIG. 1, trimming will cause the following problems.
When the zener zap trimming method is applied to a zener zap diode, that is, short-circuiting is done between the active base region 108 and the emitter region 109 to zap the PN junction, a filament 120 is formed from the emitter region 109 through the metal interconnecting layer 113-2 of the base lead region, as shown in FIG. 2. The filament 120 is an alloy of aluminum and silicon constituting the metal interconnecting layer 113-2, which is a product by a short-circuiting current running from the metal interconnecting layer 113-1 on the emitter side through the metal interconnecting layer 113-2 on the side of the base. The filament 120 is not formed in the silicon oxide film, and is formed only in the conductive layer and semiconductor layer. Therefore, as shown in FIG. 2, the filament 120 is not formed in the device isolation film 103 and the insulation film 104 thereon, and is concentratedly formed in an inner area of the polysilicon layer 105 as far as an area above the device isolation film 103 is concerned. Thereby, an excessive stress is applied to the field insulation film 106 on the polysilicon layer 105, thus producing a possibility for a damage including cracks. Furthermore, the depth of the filament 120 is less than the depth of the polysilicon layer 105 in the area above the device isolation film 103; and therefore, the resistance after trimming increases in this area. Still more, the area in which the filament 120 is formed is not stabilized, and is inclined to be differently formed by each trimming and the resistance after trimming is dispersed to a large extent. Consequently, it has been difficult to secure a sufficient reliability on the IC chip regenerated by the trimming.